Internally stacked npn with segmented collector

ABSTRACT

An integrated circuit includes a plurality of first n-type regions and a plurality of second n-type regions that each intersect a surface of a substrate. The first n-type regions are arranged in a first linear array within a first n-well and a second linear array within a second n-well. The first and second n-wells are each located within and separated by a first p-type region. The second n-type regions are located within and separated by a second p-type region. An n-type trench region is located between the first and second p-type regions. The n-type trench region extends into the substrate toward an n-type buried layer that extends under the first p-type region and the second p-type region.

CROSS-REFERENCE TO RELATED APPLICATIONS

Under 35 U.S.C. § 120, this continuation application claims the benefitof and priority to U.S. patent application Ser. No. 15/844,035, filedDec. 15, 2017 and issued as U.S. Pat. No. 10,249,607, the entirety ofwhich is hereby incorporated herein by reference. This application isrelated to U.S. patent application Ser. No. 16/371,960, filed Apr. 1,2019 and issued as U.S. Pat. No. ______, the entirety of which is herebyincorporated herein by reference.

TECHNICAL FIELD

This disclosure relates to the field of integrated circuits. Moreparticularly, this disclosure relates to stacked NPN bipolar transistorpairs in integrated circuits.

BACKGROUND

An integrated circuit may include a clamp circuit to reduce voltagestress on a protected line, for example, during an electrostaticdischarge (ESD) event. The clamp circuit may include a stacked NPNbipolar transistor pair (stacked NPN) having an upper NPN bipolartransistor (upper NPN) in series with a lower NPN bipolar transistor(lower NPN), in which a collector of the upper NPN is coupled to theprotected line, an emitter of the upper NPN is coupled to a collector ofthe lower NPN, and an emitter of the lower NPN is coupled to a groundnode of the integrated circuit. Desirable characteristics of the clampcircuit may include low resistance and uniform current distributionduring an ESD event, low area of the stacked NPN, and consistentbreakdown voltage. The integrated circuit may include analog circuitsand may include logic circuits of complementary metal oxidesemiconductor (CMOS) transistors, and it may be desirable to integratethe clamp circuit in the integrated circuit without introducingadditional process steps. However, in the integrated circuitconfiguration, it is challenging to achieve values of the resistance,current uniformity, and breakdown voltage in integrated circuits withadvanced CMOS transistors.

SUMMARY

The present disclosure introduces an integrated circuit including astacked bipolar transistor pair. The integrated circuit includes aplurality of first doped regions having a first conductivity type thateach intersect a surface of a substrate. The first doped regions arearranged in a first linear array within a second doped region having thefirst conductivity type, and a second linear array within a third dopedregion having the first conductivity type. The second and third dopedregions are each located within and separated by a fourth doped regionhaving a second conductivity type opposite the first conductivity type.A plurality of fifth doped regions having the first conductivity typeeach intersect the surface of the substrate. The fifth doped regions arelocated within and separated by a sixth doped region having the secondconductivity type. A doped trench region has the first conductivity typeand is located between the fourth and sixth doped regions. The dopedtrench region extends into the substrate toward a buried layer havingthe first conductivity type that extends under the fourth and sixthdoped regions. A method of forming the integrated circuit is disclosed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A and FIG. 1B are views of an example integrated circuit whichincludes a stacked NPN.

FIG. 2A through FIG. 2F are cross sections of an integrated circuitwhich includes a stacked NPN, depicted in stages of an example method offormation.

FIG. 3 is a top view of another example integrated circuit whichincludes a stacked NPN.

DETAILED DESCRIPTION

The present disclosure is described with reference to the attachedfigures. The figures are not drawn to scale and they are provided merelyto illustrate the disclosure. Several aspects of the disclosure aredescribed below with reference to example applications for illustration.It should be understood that numerous specific details, relationships,and methods are set forth to provide an understanding of the disclosure.The present disclosure is not limited by the illustrated ordering ofacts or events, as some acts may occur in different orders and/orconcurrently with other acts or events. Furthermore, not all illustratedacts or events are required to implement a methodology in accordancewith the present disclosure.

An integrated circuit includes a stacked NPN having a first NPN,hereinafter the upper NPN, connected to a second NPN, hereinafter thelower NPN. The upper NPN includes a first collector, hereinafter theupper collector, a first base, hereinafter the upper base, and a firstemitter, hereinafter the upper emitter. The lower NPN includes a secondcollector, hereinafter the lower collector, a second base, hereinafterthe lower base, and a second emitter, hereinafter the lower emitter. Theupper emitter may be contiguous with the lower collector. The stackedNPN may be part of a clamp circuit between a protected line and a groundline, to reduce voltage stress on the protected line during an ESDevent, for example.

The upper collector is divided into collector segments by collectorseparators; during operation of the integrated circuit, current cannotflow through the upper collector across a collector separator. Duringoperation of the integrated circuit, current flows in each collectorsegment of the upper collector toward the lower NPN. The upper collectorhas orientation directions which point along the directions of currentflow to the lower emitter. Each collector separator is aligned to theorientation directions of the adjacent collector segments, so as toallow current flow along the orientation directions. Each collectorsegment is continuous along the orientation direction through thatcollector segment. The upper collector does not have collectorseparators across the orientation directions, which can increase aresistance in the upper collector. For the purposes of this disclosure,the term “across” extends to a configuration of the collector separatorwhich would block current along the orientation direction. The collectorsegments are located on at least two opposite sides of the loweremitter. Segmenting the upper collector may reduce current crowding andthus improve current uniformity. Segmenting the upper collector asdescribed may advantageously reduce a resistance of the stacked NPNwhile providing a desired uniformity of current flow in the stacked NPN.Distributing the upper collector on opposite sides of the lower emitter,may provide a desired width of the upper collector and so reduce a totalresistance of the upper collector, compared with an upper collectorlocated on one side of the lower emitter.

The lower emitter may include an n-type semiconductor region that islaterally surrounded by a field oxide layer, with the n-typesemiconductor region directly contacting the lower base. The loweremitter may have emitter separators aligned to the orientationdirections in the collector segments nearest the emitter separators. Theemitter separators block current flow in the lower emitter across theemitter separators. The lower emitter may be free of emitter separatorsacross orientation directions in the lower emitter. Segmenting the loweremitter as such may advantageously reduce current non-uniformity due tocurrent leakage around a lateral boundary of each emitter segment.

A method of formation of the integrated circuit is disclosed. Elementsof the stacked NPN may be formed concurrently with similar elements inother circuits of the integrated circuit, advantageously reducingprocess complexity and cost.

For the purposes of this disclosure, the term “top surface” of asubstrate of the integrated circuit is understood to refer to a surfaceof the substrate at which active components such as transistors areformed. For the purposes of this disclosure, the terms “lateral” and“laterally” are understood to refer to a direction parallel to a planeof the top surface of the substrate. The term “vertical” is understoodto refer to a direction perpendicular to the plane of the top surface ofthe substrate.

It is noted that terms such as top, bottom, upper, lower, over, above,under, and below may be used in this disclosure. These terms should notbe construed as limiting the position or orientation of a structure orelement, but should be used to provide spatial relationship betweenstructures or elements.

FIG. 1A and FIG. 1B are views of an example integrated circuit whichincludes a stacked NPN. Referring to FIG. 1A, which is a top view, theintegrated circuit 100 has a substrate 102 which includes asemiconductor material such as silicon or other type IV semiconductormaterial. Other semiconductor materials are within the scope of theinstant example. The substrate 102 may be a portion of a semiconductorwafer, such as a bulk semiconductor wafer, a silicon-on-insulator (SOI)wafer, or a semiconductor wafer with a semiconductor epitaxial layer.The integrated circuit 100 includes a stacked NPN 104.

The stacked NPN 104 has an upper NPN 106 and a lower NPN 108 connectedin series. The upper NPN 106 has an upper collector 110 of n-typesemiconductor material in the substrate 102, an upper base 112 of p-typesemiconductor material in the substrate 102, and an upper emitter 114 ofn-type semiconductor material in the substrate 102. The lower NPN 108includes a lower collector 116 of n-type semiconductor material in thesubstrate 102, a lower base 118 of p-type semiconductor material in thesubstrate 102, and a lower emitter 120 of n-type semiconductor materialin the substrate 102. The upper emitter 114 may be contiguous with thelower collector 116.

The upper collector 110 is divided into first collector segments 122 ona first side of the lower NPN 108, and into second collector segments124 on a second, opposite, side of the lower NPN 108. The firstcollector segments 122 are laterally separated by first collectorseparators 126 which are aligned to first orientation directions 128 inthe first collector segments 122. The first orientation directions 128point to the lower NPN 108. In the instant example, the firstorientation directions 128 may be parallel to each other. Similarly, thesecond collector segments 124 are laterally separated by secondcollector separators 132 which are aligned to second orientationdirections 134 in the second collector segments 124. In the instantexample, the second orientation directions 134 may be parallel to eachother. Each first collector segment 122 is continuous along the firstorientation direction 128 of that first collector segment 122.Similarly, each second collector segment 124 is continuous along thesecond orientation direction 134 of that second collector segment 124.The upper collector 110 does not have collector separators 126 or 132between the collector segments 122 and 124, respectively, that arelocated across the orientation directions 128 and 134. Each of thecollector segments 122 and 124 may have first lateral dimensions, thatis, lengths, along the orientation directions 128 and 134 which aregreater than second lateral dimensions, that is, widths, that areperpendicular to the orientation directions 128 and 134. In the instantexample, the first collector separators 126 may include a field oxidelayer 130, and may include portions of the upper base 112 which extendbetween the first collector segments 122. Each of the first collectorsegments 122 and second collector segments 124 includes first n-typewells 136 in the substrate 102, and first n-type active areas 138 on thefirst n-type wells 136. The first n-type active areas 138 may be coupledto a protected line 140 through contacts 142 on the first n-type activeareas 138.

In the instant example, the upper base 112 extends under the uppercollector 110 to the upper emitter 114. The upper base 112 may include afirst p-type well in the substrate 102 laterally surrounding the firstn-type wells 136, and a first portion of p-type semiconductor materialin the substrate 102 extending below the first n-type wells 136.

In the instant example, the upper emitter 114 includes a first portionof a second n-type active area 144 on a first portion of a second n-typewell 146. The upper emitter 114 further includes a first portion of ann-type buried layer, not shown in FIG. 1A, that extends below the upperbase 112. The n-type buried layer is connected to the second n-type well146 by vertical n-type regions, also not shown in FIG. 1A. The verticaln-type regions may laterally surround deep trenches 148. The deeptrenches 148 may advantageously provide segmentation in the upperemitter 114 to improve current uniformity through the upper emitter 114.

The lower collector 116 of the instant example includes a second portionof the second n-type active area 144 on a second portion of the secondn-type well 146. The lower collector 116 further includes a secondportion of the n-type buried layer that extends below the lower base118. The lower collector 116 may be contiguous with the upper emitter114 in the second n-type active area 144, the second n-type well 146,and the n-type buried layer.

The lower base 118 may include a second p-type well in the substrate102, and a second portion of the p-type material over the second portionof the n-type buried layer in the lower collector 116. The lower base118 extends under the lower emitter 120. The lower emitter 120 may besegmented into emitter segments 150 by emitter separators 152 which arealigned to the first orientation directions 128 or to the secondorientation directions 134. The emitter separators 152 block current inthe lower emitter 120 from flowing across the emitter separators 152.The emitter separators 152 may include the field oxide layer 130, andmay include portions of the lower base 118 which extend between theemitter segments 150. The lower emitter 120 does not have emitterseparators 152 between the emitter segments 150 that are perpendicularto the orientation directions 128 and 134. Each of the emitter segments150 includes emitter n-type active areas 154 on the second p-type wellof the lower base 118. The emitter n-type active areas 154 may becoupled to a ground line 156 through additional contacts 142 on thefirst n-type active areas 138.

Dividing the upper collector 110 into the first collector segments 122and the second collector segments 124 on opposite sides of the lower NPN108 may advantageously reduce resistance in the upper collector 110 byincreasing a width of the upper collector 110 compared to a stacked NPNwith an upper collector located only on one side of a lower NPN.Locating the first collector segments 122 and the second collectorsegments 124 on opposite sides of the lower NPN 108 may advantageouslyprovide more uniform current in the lower emitter 120 compared to astacked NPN having an upper collector located only on one side of alower NPN, by flowing current into the lower NPN 108 from both sides.

Segmenting the upper collector 110 into the first collector segments 122and the second collector segments 124 may advantageously reduce currentcrowding, sometimes referred to a current hogging or filamentation, fromthe upper collector 110 into the upper base 112. Having no collectorseparators 126 or 132 in the upper collector 110 across the orientationdirections 128 and 134, respectively, may advantageously improve currentuniformity for versions of the integrated circuit 100 which havesignificant perimeter current components in active areas, that is, wherecurrent around a perimeter of an active area is higher than currentthrough the middle of the active area. Generally, depths of heavilydoped regions, such as source and drain regions, in active areas havebecome more shallow as technology nodes for logic circuits haveprogressed, and perimeter current as a fraction of total current hasincreased as a result. Similar benefits may accrue from segmenting thelower emitter 120 into the emitter segments 150 with the emitterseparators 152 aligned to, and not perpendicular to, the orientationdirections 128 and 134.

The stacked NPN 104 is surrounded by an isolation structure 158 whichextends around the stacked NPN 104. One manifestation of the isolationstructure 158 will be described in the instant example. Otherarchitectures and configurations for the isolation structure 158 arewithin the scope of the instant example.

Referring to FIG. 1B, which is a cross section, the integrated circuit100 has the substrate 102 which includes the semiconductor material 160referred to, but not shown, in FIG. 1A. In the instant example, thesemiconductor material 160 is p-type, and may be a portion of a basewafer.

The upper collector 110 of the upper NPN 106 includes the first n-typewells 136 in the substrate 102, and the first n-type active areas 138 onthe first n-type wells 136. The first n-type active areas 138 areseparated by the field oxide layer 130. The field oxide layer 130 mayhave a shallow trench isolation (STI) structure, may have a localoxidation of silicon (LOCOS) structure, or may have another structure.In the instant example, the field oxide layer 130 has an STI structure,which has silicon dioxide disposed in isolation trenches in thesubstrate 102; the isolation trenches have substantially straight sidesand are wider at tops of the isolation trenches than at bottoms of theisolation trenches. A top surface of the field oxide layer 130 with anSTI structure may be substantially coplanar with a top surface of thesubstrate 102 adjacent to the field oxide layer 130. A LOCOS structurehas a layer of silicon dioxide with tapered edges, sometimes referred toas birds beaks; approximately half of the silicon dioxide is locatedbelow the top surface of the adjacent substrate 102 and the remainder islocated higher than the top surface.

The upper base 112 includes the first portion of the semiconductormaterial 160, which is p-type, the first p-type well 162 which laterallysurrounds the first n-type wells 136, and upper base contact regions164, which are p-type, on the first p-type well 162.

The upper emitter 114 includes the first portion of the second n-typeactive area 144 on the first portion of the second n-type well 146. Theupper emitter 114 further includes the first portion of the n-typeburied layer 166 which extends below the upper base 112. The n-typeburied layer 166 is connected to the second n-type well 146 by verticaln-type regions 168 which surround the deep trenches 148 of FIG. 1A, ifpresent.

The lower collector 116 includes the second portion of the second n-typeactive area 144 on the second portion of the second n-type well 146. Thelower collector 116 further includes the second portion of the n-typeburied layer 166 which extends below the lower base 118. The verticaln-type regions 168 connect the second portion of the second n-type well146 with the second portion of the n-type buried layer 166.

The lower base 118 includes the second portion of the semiconductormaterial 160 which is over the second portion of the n-type buried layer166, and the second p-type well 170 below the lower emitter 120.

The lower emitter 120 includes the emitter n-type active areas 154 onthe second p-type well 170. The emitter n-type active areas 154 arelaterally surrounded by lower base contact regions 172, which arep-type, on the second p-type well 170. The emitter n-type active areas154 are laterally separated from the lower base contact regions 172 bythe field oxide layer 130.

The isolation structure 158 may include a deep trench 174 with a silicondioxide liner 176 and a core 178 of p-type polycrystalline silicon whichmakes contact with the semiconductor material 160 below the n-typeburied layer 166. Vertical n-type regions 180 may be located around thedeep trench 174. Other architectures for the isolation structure 158,such as deep n-type regions referred to as sinkers, are within the scopeof the instant example.

A dielectric layer 182 is disposed over the substrate 102. Thedielectric layer 182 may be, for example, a pre-metal dielectric (PMD)layer 182 which may include one or more sub-layers of dielectricmaterial, for example, a PMD liner of silicon nitride directly over thesubstrate 102, a main dielectric layer of silicon dioxide-based materialsuch as phosphorus silicate glass (PSG) or boron phosphorus silicateglass (BPSG) on the PMD liner, and a cap layer of silicon dioxide,silicon nitride, silicon oxynitride, silicon carbide or silicon carbidenitride on the main dielectric layer. Other layer structures andcompositions for the dielectric layer 182 are within the scope of theinstant example.

Contacts 142 are disposed through the dielectric layer 182 to provideelectrical connections to the elements of the stacked NPN 104. Thecontacts 142 may include a liner containing titanium, a barrier layerincluding tantalum nitride or titanium nitride on the liner, and a coreof tungsten on the barrier layer. The protected line 140, which may bean interconnect line on the dielectric layer 182, is coupled to theupper collector 110 through instances of the contacts 142. Similarly,the ground line 156, which may also be an interconnect line on thedielectric layer 182, is coupled to the lower emitter 120 throughinstances of the contacts 142. Any of the upper base 112, the upperemitter 114 and the lower collector 116, and the lower base 118 may becoupled to trigger circuits through instances of the contacts 142.

FIG. 2A through FIG. 2F are cross sections of an integrated circuitwhich includes a stacked NPN, depicted in stages of an example method offormation. Referring to FIG. 2A, the integrated circuit 200 is formed inand on a substrate 202 which includes semiconductor material 260. Thesubstrate 202 may be, for example, a semiconductor wafer. In the instantexample, the semiconductor material 260 is p-type.

An n-type buried layer 266 is formed in the substrate 202 in an area forthe stacked NPN 204. The n-type buried layer 266 may be formed byimplanting n-type dopants such as antimony and possibly arsenic into abase portion of the substrate 202, heating the base portion to diffusethe implanted n-type dopants, and forming an epitaxial layer on the baseportion. The n-type dopants may be implanted with a total dose of 5×10″cm⁻² to 3×10¹⁵ cm⁻², for example. During formation of the epitaxiallayer, the implanted n-type dopants diffuse further downward into thebase portion, and upward into the epitaxial layer, to form the n-typeburied layer 266. The base portion and the epitaxial layer provide thesubstrate 202. The epitaxial layer includes p-type semiconductormaterial which is part of the semiconductor material 260. Other methodsof forming the n-type buried layer 266, such as implanting n-typedopants at high energy into the substrate 202, are within the scope ofthe instant example. The n-type buried layer 266 of the instant exampleextends continuously across an area for an upper NPN 206 of the stackedNPN 204 and an area for a lower NPN 208 of the stacked NPN 204.

Referring to FIG. 2B, a deep trench mask 286 is formed over thesubstrate 202. The deep trench mask 286 may include hard mask materialsuch as silicon dioxide or silicon nitride. The deep trench mask 286exposes an area for a deep trench 274 of an isolation structure 258. Thearea for the deep trench 274 of the isolation structure 258 laterallysurrounds the area for the stacked NPN 204. The deep trench mask 286also exposes areas for a plurality of deep trenches 248 extending intoan area for an upper emitter 214 of the upper NPN 206 and into an areafor a lower collector 216 of the lower NPN 208. The areas for the upperemitter 214 and the lower collector 216 are contiguous. The areas forthe deep trenches 248 extend in a line perpendicular to the plane ofFIG. 2B. The deep trench 274 and the plurality of deep trenches 248 maybe formed concurrently. The deep trench 274 and the plurality of deeptrenches 248 may be formed by any of several deep reactive ion etch(DRIE) processes, including a continuous DRIE process which forms aprotective polymer on sidewalls of the deep trench 274 and the pluralityof deep trenches 248 while simultaneously etching semiconductor material260 from bottoms of the deep trench 274 and the plurality of deeptrenches 248, or a two-step DRIE process, sometimes referred to as aBosch DRIE process, which forms the protective polymer and etches thesemiconductor material 260 in separate alternating steps.

The deep trench 274 of the isolation structure 258 laterally surroundsthe area for the stacked NPN 204 and intersects the n-type buried layer266 around a perimeter of the area for the stacked NPN 204. The deeptrenches 248 extend in a line perpendicular to the plane of FIG. 2B, andthe instance of the deep trenches 248 shown in FIG. 2B is out of theplane of FIG. 2B and so is depicted in dashed lines. The deep trench 274and the plurality of deep trenches 248 are formed to extend below then-type buried layer 266.

N-type dopants 288 are implanted into the substrate 202 along sidewallsof the deep trench 274 and the plurality of deep trenches 248 to formvertical implanted layers 290 along the sidewalls of the deep trench 274and the plurality of deep trenches 248 down to the n-type buried layer266. The n-type dopants 288 may include phosphorus and arsenic, and maybe implanted in several steps at tilt angles of 20 degrees to 30 degreesfrom a vertical axis perpendicular to a top surface of the substrate202. The n-type dopants 288 may be implanted at a total dose of 3×10¹⁴cm⁻² to 3×10¹⁵ cm⁻², for example, to attain a desired conductivity insubsequently-formed vertical n-type regions.

Referring to FIG. 2C, silicon dioxide liners 276 are formed on sidewallsof the deep trench 274 and the plurality of deep trenches 248. Thesilicon dioxide liners 276 may be formed, for example, by a thermaloxidation process. The implanted n-type dopants 288 of FIG. 2B in thevertical implanted layers 290 of FIG. 2B are activated to form verticaln-type regions 280 along the deep trench 274, and form a continuousvertical n-type region 268 around the plurality of deep trenches 248.The thermal oxidation process may provide adequate thermal profile toactivate the implanted n-type dopants 288; otherwise, an additionalanneal may be employed.

Cores 278 are formed on the silicon dioxide liners 276 in the deeptrench 274 and the plurality of deep trenches 248. The cores 278 mayinclude p-type polycrystalline silicon or other electrically conductivematerial. The cores 278 make electrical connections to the semiconductormaterial 260 below the n-type buried layer 266. The deep trench mask 286is removed. The deep trench mask 286 may be removed prior to forming thecores 278 or after forming the cores 278.

Referring to FIG. 2D, field oxide layer 230 is formed on the substrate202. The field oxide layer 230 may be formed by an STI process, by aLOCOS process, or by another process. An example STI process includesforming a CMP stop layer of silicon nitride over the substrate 202,etching isolation trenches through the CMP stop layer and into thesubstrate 202, and filling the isolation trenches with silicon dioxideusing a plasma enhanced chemical vapor deposition (PECVD) process usingtetraethyl orthosilicate (TEOS), a high density plasma (HDP) process, ahigh aspect ratio process (HARP) using TEOS and ozone, an atmosphericchemical vapor deposition (APCVD) process using silane, or asubatmospheric chemical vapor deposition (SACVD) process usingdichlorosilane. Excess silicon dioxide is removed from over the CMP stoplayer by an oxide chemical mechanical polish (CMP) process, and the CMPstop layer is subsequently removed, leaving the field oxide layer 230.An example LOCOS process includes forming a silicon nitride mask layerover a layer of LOCOS pad oxide over the substrate 202. The siliconnitride mask layer is removed in areas for the field oxide layer 230,exposing the LOCOS pad oxide. Silicon dioxide is formed in the areasexposed by the silicon nitride mask layer by thermal oxidation, to formthe field oxide layer 230. The silicon nitride mask layer issubsequently removed, leaving the field oxide layer 230 in place.

The field oxide layer 230 is located so as to provide parts of collectorseparators in the area for the upper collector 210 of the upper NPN 206.The field oxide layer 230 also laterally separates the areas for theupper collector 210, an upper base 212, and the upper emitter 214, allof the upper NPN 206, and the lower collector 216, a lower base 218 anda lower emitter 220, all of the lower NPN 208. In the instant example,the field oxide layer 230 does not separate the area for the upperemitter 214 from the lower collector 216.

Referring to FIG. 2E, a first p-type well 262 is formed in the substrate202 as part of the upper base 212. A second p-type well 270 is formed inthe substrate 202 as part of the lower base 218. The first p-type well262 and the second p-type well 270 may be formed concurrently with otherp-type wells containing n-channel metal oxide semiconductor (NMOS)transistors in the integrated circuit 200. The first p-type well 262 andthe second p-type well 270 may be formed by implanting p-type dopantssuch as boron into the substrate 202 at a total dose of 3×10¹³ cm⁻² to1×10¹⁴ cm⁻², for example.

A plurality of first n-type wells 236, one of which is shown in FIG. 2E,is formed in the substrate 202 as part of the upper collector 210. Asecond n-type well 246 is formed in the substrate 202 as part of theupper emitter 214 and part of the lower collector 216. The first n-typewells 236 and the second n-type well 246 may be formed by implantingn-type dopants such as phosphorus and arsenic into the substrate 202 ata total dose of 3×10¹³ cm⁻² to 1×10¹⁴ cm⁻², for example. The firstn-type wells 236 and the second n-type well 246 may be formedconcurrently with other n-type wells containing p-channel metal oxidesemiconductor (PMOS) transistors in the integrated circuit 200.

Referring to FIG. 2F, n-type regions are formed concurrently in thesubstrate 202 to provide source and drain regions for NMOS transistors,contact regions for n-type wells, and such. The n-type regions includefirst n-type active areas 238 on the first n-type wells 236 in the uppercollector 210, a second n-type active area 244 on the second n-type well246 in the upper emitter 214 and the lower collector 216, and emittern-type active areas 254 of the lower emitter 220 on the second p-typewell 270 of the lower base 218. The n-type regions may be formed byimplanting n-type dopants such as phosphorus, arsenic, and antimony,into the substrate 202 at a total dose of 3×10¹⁴ cm⁻² to 1×10¹⁶ cm⁻² forexample.

P-type regions are formed concurrently in the substrate 202 to providesource and drain regions for PMOS transistors, contact regions forp-type wells, and such. The p-type regions include upper base contactregions 264 on the first p-type well 262 of the upper base 212, andlower base contact regions 272 on the second p-type well 270 of thelower base 218. The p-type regions may be formed by implanting p-typedopants such as boron, gallium, and possibly indium, into the substrate202 at a total dose of 3×10¹⁴ cm⁻² to 1×10¹⁶ cm⁻², for example.

Forming the elements of the stacked NPN 204, such as the p-type wells262 and 270, the n-type wells 236 and 246, the n-type regions 238, 244,and 254, and the p-type regions 264 and 272, concurrently withcorresponding elements of the NMOS transistors and PMOS transistors mayadvantageously reduce fabrication cost and complexity of the integratedcircuit 200.

FIG. 3 is a top view of another example integrated circuit whichincludes a stacked NPN. The integrated circuit 300 is formed on asubstrate 302, for example, as described in reference to FIG. 1A andFIG. 1B. In the instant example, the stacked NPN 304 has a concentricconfiguration, in which an upper collector 310 has collector segments322 arranged radially at least partially around a lower emitter 320. Thecollector segments 322 are disposed on at least two opposite sides ofthe lower emitter 320; in the instant example, the collector segments322 are disposed on all sides of the lower emitter 320. Current flowsthrough the collector segments 322 toward the lower emitter 320, asindicated by orientation directions 328. Adjacent pairs of the collectorsegments 322 are separated by collector separators 326 which are alignedto orientation directions 328 in the collector segments 322. Thecollector separators 326 block current in the upper collector 310 fromflowing across the collector separators 326. The collector separators326 may include field oxide, p-type active areas, or other currentblocking structures. Each collector segment 322 is continuous along theorientation direction 328 of that collector segment 322. The uppercollector 310 does not have separators between adjacent pairs of thecollector segments 322 across the orientation directions 328 in theadjacent collector segments 322. The concentric configuration of theupper collector 310 may advantageously improve a current capacity of thestacked NPN 304, because the concentric configuration provides a greaterwidth for the upper collector 310 while maintaining a low resistancepath to the lower emitter 320.

The lower emitter 320 may optionally be divided into emitter segments350, to reduce current crowding in the lower emitter 320. The loweremitter 320 is separated from the upper collector 310 by a combinedupper emitter 314 and lower collector 316, disposed around the loweremitter 320. The combined upper emitter 314 and lower collector 316 maybe segmented by deep trenches 348 to reduce current crowding in thecombined upper emitter 314 and lower collector 316.

The upper collector 310 may be connected to a protected line 340 whichextends over the collector segments 322. Similarly, the lower emitter320 may be connected to a ground line 356 which extends over the emittersegments 350. The concentric configuration, depicted in FIG. 3, may beconducive to short distances between the upper collector 310 and theprotected line 340, and between the lower emitter 320 and the groundline 356, as depicted in FIG. 3, advantageously reducing a resistancebetween the protected line 340 and the ground line 356 through thestacked NPN 304.

While various embodiments of the present disclosure have been describedabove, it should be understood that they have been presented by way ofexample only and not limitation. Numerous changes to the disclosedembodiments can be made in accordance with the disclosure herein withoutdeparting from the spirit or scope of the disclosure. Thus, the breadthand scope of the present invention should not be limited by any of theabove described embodiments. Rather, the scope of the disclosure shouldbe defined in accordance with the following claims and theirequivalents.

1-19: (canceled)
 20. An electronic device, comprising: an emitterregion, a collector region and a base region formed within asemiconductor substrate having a first conductivity type; a deep-dopedregion having a second opposite conductivity type, the deep-doped regionextending to a buried layer having the second conductivity type thatextends under the emitter region, the collector region and the baseregion; an array of deep trench islands within the deep-doped region,the deep trench islands conductively isolated from the buried layer andlocated between the collector region and the emitter region such thatcurrent between the connector region and the emitter region passesbetween the deep trench islands; and the collector region includescollector contacts arranged as a plurality of linear arrays, each lineararray separated from a nearest-neighbor linear array by a dielectricisolation structure.
 21. The device of claim 20, wherein the lineararrays are aligned along a direction of current between the emitterregion and the collector region.
 22. The device of claim 20, furtherwherein the linear arrays of collector contacts are arranged such thatcurrent between each linear array and the emitter region follows adirect path between corresponding pairs of nearest-neighbor deep trenchislands.
 23. The device of claim 20, wherein the linear arrays arealigned along a direction of current between the emitter region and thecollector region.
 24. The device of claim 20, wherein the deep trenchislands each include a polysilicon core that conductively connects tothe semiconductor substrate below the buried layer.
 25. The device ofclaim 20, wherein the emitter includes a doped region of the secondconductivity type located within a well region of the first conductivitytype.
 26. The device of claim 20, wherein the base region includes awell region of the first conductivity type that surrounds a well regionof the second conductivity type.
 27. The device of claim 20, wherein thecollector region includes a well region of the first second conductivitytype surrounded by a well region of the second conductivity type. 28.The device of claim 20, wherein the deep trench islands each include aconductive core laterally surrounded by an insulting liner.
 29. Thedevice of claim 20, wherein the first conductivity type is P-type andthe second conductivity type is N-type.
 30. An electronic device,comprising: an emitter region, a collector region and a base regionformed within a semiconductor substrate having a first conductivitytype; a deep-doped region having a second opposite conductivity type,the deep-doped region extending to a buried layer having the secondconductivity type that extends under the emitter region, the collectorregion and the base region; an array of deep trench islands within thedeep-doped region, the deep trench islands conductively isolated fromthe buried layer and located between the collector region and theemitter region such that current between the connector region and theemitter region passes between the deep trench islands; and the emitterregion includes emitter contacts arranged as a plurality of lineararrays, each linear array separated from a nearest-neighbor linear arrayby a dielectric isolation structure.
 31. The device of claim 30, whereinthe linear arrays are aligned along a direction of current between theemitter region and the collector region.
 32. The device of claim 30,further wherein the linear arrays of emitter contacts are arranged suchthat current between each linear array and the collector region followsa direct path between corresponding pairs of nearest-neighbor deeptrench islands.
 33. A method of forming an electronic device,comprising: forming an emitter region, a collector region and a baseregion within a semiconductor substrate having a first conductivitytype; forming a deep-doped region having a second opposite conductivitytype within the substrate, the deep-doped region extending to a buriedlayer having the second conductivity type that extends under the emitterregion, the collector region and the base region; and forming an arrayof deep trench islands within the deep-doped region, the deep trenchislands conductively isolated from the buried layer and located betweenthe collector region and the emitter region such that current betweenthe connector region and the emitter region passes between the deeptrench islands, wherein the collector region includes collector contactsarranged as a plurality of linear arrays, each linear array separatedfrom a nearest-neighbor linear array by a dielectric isolationstructure.
 34. The method of claim 33, wherein the linear arrays arealigned along a direction of current between the emitter region and thecollector region.
 35. The method of claim 33, further wherein the lineararrays of collector contacts are arranged such that current between eachlinear array and the emitter region follows a direct path betweencorresponding pairs of nearest-neighbor deep trench islands.
 36. Themethod of claim 33, wherein the deep trench islands each include apolysilicon core that conductively connects to the semiconductorsubstrate below the buried layer.
 37. The method of claim 33, whereinthe emitter includes a doped region of the second conductivity typelocated within a well region of the first conductivity type.
 38. Themethod of claim 33, wherein the base region includes a well region ofthe first conductivity type that surrounds a well region of the secondconductivity type.
 39. The method of claim 33, wherein the collectorregion includes a well region of the first second conductivity typesurrounded by a well region of the second conductivity type.
 40. Themethod of claim 33, wherein the deep trench islands each include aconductive core laterally surrounded by an insulting liner.
 41. Themethod of claim 33, wherein the first conductivity type is P-type andthe second conductivity type is N-type.
 42. An electronic device,comprising: an emitter region, a collector region and a base regionformed within a semiconductor substrate having a first conductivitytype; a deep-doped region having a second opposite conductivity type,the deep-doped region extending to a buried layer having the secondconductivity type that extends under the emitter region, the collectorregion and the base region; an array of deep trench islands within thedeep-doped region, the deep trench islands conductively isolated fromthe buried layer and located between the collector region and theemitter region such that current between the connector region and theemitter region passes between the deep trench islands.